Multiple Constraints Driven System-on-Chip Test Time Optimization
The cost oftesting SOCs (systems-on-chip) is highly related to the testapplication time. The problem is that the test application timeincreases as the technology makes it possible to design highlycomplex chips. These complex chips include a high number of faultsites, which need a high test data volume for testing, and the hightest data volume leads to long test application times. For modularcore-b
