A Technology Agnostic Approach for Standard-cell Layout Design Automation
The logic scaling following Moores law has reached a level where System on Chips (SoCs) commonly contains millions of standard cells. The sheer amount implies that even small optimizations on a standard cell can have a significant effect on the SoC performance. To ensure the performance of standard cells, many of these are hand-drawn. This is a tedious task that needs to be done every time a new p
