Gate-Induced Fermi Level Tuning in InP Nanowires at Efficiency Close to the Thermal Limit.
As downscaling of semiconductor devices continues, one or a few randomly placed dopants may dominate the characteristics. Furthermore, due to the large surface-to-volume ratio of one-dimensional devices, the position of the Fermi level is often determined primarily by surface pinning, regardless of doping level. In this work, we investigate the possibility of tuning the Fermi level dynamically wit