Electronic structure of [100]-oriented free-standing InAs and InP nanowires with square and rectangular cross sections

We report on a theoretical study of the electronic structure of free-standing InAs and InP nanowires grown along the [100] crystallographic direction, based on an atomistic tight-binding approach. The band structure and wave functions for nanowires with both square (nanowires) and rectangular (nanobelts) cross sections are calculated. A comparison is made between the calculations for InAs, InP, an

Diurnal variations of summer precipitation in Beijing area and the possible effect of topography and urbanization

Development of nanoporous gold electrode for electrochemical methods applications

Fused modality or confused modality?

Status of the FEL Test Facility at MAX-lab

Disposal of waste electrical and electronic equipment: A household survey of past behaviors and future preferences in Thailand

Households play a crucial role in the management of waste electrical and electronic equipment (WEEE). As waste generators, their decisions at the point of disposal hold a key to a success of WEEE collection. This article presents main findings from a national survey in Thailand about the reported disposal behaviors in the past and the stated disposal preferences in the future. The survey covered t

Nucleation and initial stages of growth of GaN nanowires for LEDs by selective-area MOVPE

Implementation Issues for acoustic echo cancellers

The high computational complexity of acoustic echo cancellation algorithms requires application specific implementations to sustain real time signal processing with affordable power consumption. This is especially true for systems where a delayless approach is considered important, e.g. wireless communication systems. The proposed paper presents architectural considerations to reach a feasible har

Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias

In this paper we have proposed a test cost model for core-based 3D Stacked ICs (SICs) connected by Through Silicon Vias (TSVs). Unlike in the case of non-stacked chips, where the test flow is well defined by applying the same test schedule both at wafer sort and at package test, the most cost-efficient test flow for 3D TSV-SICs is yet undefined. Therefore, analysing the various alternatives of tes

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Stability Analysis of an On-Line Algorithm for Torque Limited Path Following

A Digital PLL Made from Standard Cells

Direct and inverse problems in bianisotropic waveguides

Heterotopia and landfills

Perception of own death risk: An analysis of road-traffic and overall mortality risks

Electrical Design Considerations in Powerformer™

Diversity and Performance - a study of Nordic board composition

New Tuning Methods for PID Controllers

Stress-strain relationship of drying wood. Part I: Development of a constitutive model.

Analysis of phosphate uptake kinetics in chemostat culture of Saccharomyces cerevisiae