Test Planning for 3D SICs using ILP
In this paper we propose a test planning scheme for corebased 3D stacked integrated circuits where the total test cost for wafer sort of each individual chip and the test cost of the complete stack at package test is minimized. We use an Integer Linear Programming (ILP) model to find the optimal test cost, which is given as the weighted sum of the test time and the test access mechanism (TAM). As